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sn55lvds31, SN65LVDS31, sn65lvds3487, sn65lvds9638 high-speed differential line drivers slls261f july 1997 revised march 2000 1 post office box 655303 ? dallas, texas 75265 meets or exceeds the requirements of ansi tia/eia-644 standard low-voltage differential signaling with typical output voltage of 350 mv and a 100- w load typical output voltage rise and fall times of 500 ps (400 mbps) typical propagation delay times of 1.7 ns operates from a single 3.3-v supply power dissipation 25 mw typical per driver at 200 mhz driver at high impedance when disabled or with v cc = 0 bus-terminal esd protection exceeds 8 kv low-voltage ttl (lvttl) logic input levels pin-compatible with the am26ls31, mc3487, and m a9638 description the sn55lvds31, SN65LVDS31, sn65lvds3487, and sn65lvds9638 are differential line drivers that implement the electrical characteristics of low-voltage differential signaling (lvds). this signaling technique lowers the output voltage levels of 5 v differential standard levels (such as tia/eia-422b) to reduce the power, increase the switching speeds, and allow operation with a 3.3-v supply rail. any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mv into a 100- w load when enabled. the intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 w . the transmission media may be printed-circuit board traces, backplanes, or cables. the ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. the SN65LVDS31, sn65lvds3487, and sn65lvds9638 are characterized for operation from 40 c to 85 c. the sn55lvds31 is characterized for operation from 55 c to 125 c. copyright ? 2000, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1a 1y 1z g 2z 2y 2a gnd v cc 4a 4y 4z g 3z 3y 3a sn55lvds31 ... j or w SN65LVDS31d (marked as lvds31 or 65lvds31 ) (top view) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1a 1y 1z 1,2en 2z 2y 2a gnd v cc 4a 4y 4z 3,4en 3z 3y 3a sn65lvds3487d (marked as lvds3487 or 65lvds3487 ) (top view) 1 2 3 4 8 7 6 5 v cc 1a 2a gnd 1y 1z 2y 2z sn65lvds9638d (marked as dk638 or lvds38 ) sn65lvds9638dgn (marked as l38 ) (top view) 19 20 1 32 17 18 16 15 14 13 12 11 9 10 5 4 6 7 8 4y 4z nc g 3z 1z g nc 2z 2y 1y 1a nc v 4a gnd nc 3a 3y 2a sn55lvds31fk (top view) cc
sn55lvds31, SN65LVDS31, sn65lvds3487, sn65lvds9638 high-speed differential line drivers slls261f july 1997 revised march 2000 2 post office box 655303 ? dallas, texas 75265 available options package t a small outline (d) msop (dgn) chip carrier (fk) ceramic dip (j) flat pack (w) SN65LVDS31d e e e e 40 c to 85 c sn65lvds3487d e e e e sn65lvds9638d sn65lvds9638dgn e e e 55 c to 125 c e e sn55lvds31fk sn55lvds31j sn55lvds31w logic symbol 2 sn55lvds31, SN65LVDS31 4z 4y 3z 3y 2z 2y 1z 1y 4a 3a 2a 1a g g 13 14 11 10 5 6 3 2 15 9 7 1 12 4 1 en 2 this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. 'lvds31 logic diagram (positive logic) 4z 4y 3z 3y 2z 2y 1z 1y 13 14 11 10 5 6 3 2 4a 3a 2a 1a g g 15 9 7 1 12 4
sn55lvds31, SN65LVDS31, sn65lvds3487, sn65lvds9638 high-speed differential line drivers slls261f july 1997 revised march 2000 3 post office box 655303 ? dallas, texas 75265 logic symbol 2 en en 4z 4y 3z 3y 2z 2y 1z 1y 15 9 12 7 1 4 4a 3a 3, 4en 2a 1a 1, 2en 13 14 11 10 5 6 3 2 sn65lvds3487 2 this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. 'lvds3487 logic diagram (positive logic) 4z 4y 3z 3y 2z 2y 1z 1y 13 14 11 10 5 6 3 2 4a 3a 2a 1a 15 9 1 4 7 12 3,4en 1,2en logic symbol 2 2z 2y 1z 1y 3 2 2a 1a 5 6 7 8 sn65lvds9638 2 this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. 'lvds9638 logic diagram (positive logic) 2z 2y 1z 1y 5 6 7 8 2a 1a 2 3
sn55lvds31, SN65LVDS31, sn65lvds3487, sn65lvds9638 high-speed differential line drivers slls261f july 1997 revised march 2000 4 post office box 655303 ? dallas, texas 75265 function tables sn55lvds31, SN65LVDS31 input enables outputs a g g y z h h x h l l h x l h h x l h l l x l l h x l h z z open h x l h open x l l h h = high level, l = low level, x = irrelevant, z = high impedance (off) sn65lvds3487 input enable outputs a en y z h h h l l h l h x l z z open h l h h = high level, l = low level, x = irrelevant, z = high impedance (off) sn65lvds9638 input outputs a y z h h l l l h open l h h = high level, l = low level
sn55lvds31, SN65LVDS31, sn65lvds3487, sn65lvds9638 high-speed differential line drivers slls261f july 1997 revised march 2000 5 post office box 655303 ? dallas, texas 75265 equivalent input and output schematic diagrams 7 v 300 k w 50 w v cc input v cc 5 w 7 v y or z output equivalent of each a input equivalent of g, g , 1,2en or 3,4en inputs typical of all outputs 7 v 50 w v cc input 10 k w absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range, v cc (see note 1) 0.5 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous total power dissipation see dissipation rating table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltages, except differential i/o bus voltages, are with respect to the network ground terminal. dissipation rating table package t a 25 c power rating derating factor 3 above t a = 25 c t a = 70 c power rating t a = 85 c power rating t a = 125 c power rating d (8) 725 mw 5.8 mw/ c 464 mw 377 mw e d (16) 950 mw 7.6 mw/ c 608 mw 494 mw e dgn 2.14 w 17.1 mw/ c 1.37 w 1.11 w e fk 1375 mw 11.0 mw/ c 880 mw 715 mw 275 mw j 1375 mw 11.0 mw/ c 880 mw 715 mw 275 mw w 1000 mw 8.0 mw/ c 640 mw 520 mw 200 mw 3 this is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. recommended operating conditions min nom max unit supply voltage, v cc 3 3.3 3.6 v high-level input voltage, v ih 2 v low-level input voltage, v il 0.8 v o p erating free air tem p erature t a sn65 prefix 40 85 c operating free - air temperat u re , t a sn55 prefix 55 125 c
sn55lvds31, SN65LVDS31, sn65lvds3487, sn65lvds9638 high-speed differential line drivers slls261f july 1997 revised march 2000 6 post office box 655303 ? dallas, texas 75265 sn65lvdsxxxx electrical characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions SN65LVDS31, '3487, ' 9638 unit min typ 2 max

247 340 454 mv d v od change in differential output voltage magnitude between logic states r l = 100 w , see figure 2 50 50 mv v oc(ss) steady-state common-mode output voltage see figure 3 1.125 1.2 1.375 mv d v oc(ss) change in steady-state common-mode output voltage between logic states see figure 3 50 50 v v oc(pp) peak-to-peak common-mode output voltage g 50 150 mv SN65LVDS31 v i = 0.8 v or 2 v, no load enabled, 9 20 ma i cc su pp ly current SN65LVDS31, '3487 v i = 0.8 or 2 v, enabled r l = 100 w , 25 35 ma i cc su ly current v i = 0 or v cc , disabled 0.25 1 ma sn65lvds9638 v i =08vor2v no load 4.7 8 ma sn65lvds9638 v i = 0 . 8 v or 2 v r l = 100 w 9 13 ma i ih high-level input current v ih = 2 4 20 m a i il low-level input current v il = 0.8 v 0.1 10 m a i os short circuit out p ut current v o(y) or v o(z) = 0 4 24 ma i os short - circ u it o u tp u t c u rrent v od = 0 12 ma i oz high-impedance output current v o = 0 or 2.4 v 1 m a i o(off) power-off output current v cc = 0, v o = 2.4 v 1 m a c i input capacitance 3 pf 2 all typical values are at t a = 25 c and with v cc = 3.3 v. sn65lvdsxxxx switching characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions SN65LVDS31, '3487, ' 9638 unit min typ 2 max t plh propagation delay time, low-to-high-level output 0.5 1.4 2 ns t phl propagation delay time, high-to-low-level output 1 1.7 2.5 ns t r differential output signal rise time (20% to 80%) r l = 100 w , c l = 10 pf, 0.4 0.5 0.6 ns t f differential output signal fall time (80% to 20%) l , l , see figure 2 0.4 0.5 0.6 ns t sk(p) pulse skew (|t phl t plh |) 0.3 0.6 ns t sk(o) channel-to-channel output skew 3 0 0.3 ns t sk(pp) part-to-part skew 800 ps t pzh propagation delay time, high-impedance-to-high-level output 5.4 15 ns t pzl propagation delay time, high-impedance-to-low-level output see figure 4 2.5 15 ns t phz propagation delay time, high-level-to-high-impedance output see fig u re 4 8.1 15 ns t plz propagation delay time, low-level-to-high-impedance output 7.3 15 ns 2 all typical values are at t a = 25 c and with v cc = 3.3 v. 3 t sk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. t sk(pp) is the magnitude of the different in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, same temperature, and have identical packages and test circuits.
sn55lvds31, SN65LVDS31, sn65lvds3487, sn65lvds9638 high-speed differential line drivers slls261f july 1997 revised march 2000 7 post office box 655303 ? dallas, texas 75265 sn55lvds31 electrical characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions sn55lvds31 unit parameter test conditions min typ 2 max unit

247 340 454 mv d v od change in differential output voltage magnitude between logic states r l = 100 w , see figure 2 50 50 mv v oc(ss) steady-state common-mode output voltage 1.125 1.2 1.375 v d v oc(ss) change in steady-state common-mode output voltage between logic states see figure 3 50 50 mv v oc(pp) peak-to-peak common-mode output voltage 50 150 mv v i = 0.8 v or 2 v, no load enabled, 9 20 ma i cc supply current v i = 0.8 or 2 v, enabled r l = 100 w , 25 35 ma v i = 0 or v cc , disabled 0.25 1 ma i ih high-level input current v ih = 2 4 20 m a i il low-level input current v il = 0.8 v 0.1 10 m a i os short circuit out p ut current v o(y) or v o(z) = 0 4 24 ma i os short - circ u it o u tp u t c u rrent v od = 0 12 ma i oz high-impedance output current v o = 0 or 2.4 v 1 m a i o(off) power-off output current v cc = 0, v o = 2.4 v 4 m a c i input capacitance 3 pf 2 all typical values are at t a = 25 c and with v cc = 3.3 v. sn55lvds31 switching characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions sn55lvds31 unit parameter test conditions min typ 2 max unit t plh propagation delay time, low-to-high-level output 0.5 1.4 4 ns t phl propagation delay time, high-to-low-level output 1 1.7 4.5 ns t r differential output signal rise time (20% to 80%) r l = 100 w , c l = 10 pf, 0.4 0.5 1 ns t f differential output signal fall time (80% to 20%) l , l , see figure 2 0.4 0.5 1 ns t sk(p) pulse skew (|t phl t plh |) 0.3 0.6 ns t sk(o) channel-to-channel output skew 3 0.3 0.6 ns t pzh propagation delay time, high-impedance-to-high-level output 5.4 15 ns t pzl propagation delay time, high-impedance-to-low-level output see figure 4 2.5 15 ns t phz propagation delay time, high-level-to-high-impedance output see fig u re 4 8.1 17 ns t plz propagation delay time, low-level-to-high-impedance output 7.3 15 ns 2 all typical values are at t a = 25 c and with v cc = 3.3 v. 3 t sk(o ) is the maximum delay time difference between drivers on the same device.
sn55lvds31, SN65LVDS31, sn65lvds3487, sn65lvds9638 high-speed differential line drivers slls261f july 1997 revised march 2000 8 post office box 655303 ? dallas, texas 75265 parameter measurement information v i a (v oy + v oz )/2 i oz i oy y z v od v oy v oc i i v oz figure 1. voltage and current definitions y z v od input (see note a) c l = 10 pf (2 places) (see note b) 100 1 % 2 v 1.4 v 0.8 v t plh t phl 100% 80% 20% 0% input v od 0 t f t r notes: a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, pulse repetition rate (prr) = 50 mpps, pulse width = 10 0.2 ns. b. cl includes instrumentation and fixture capacitance within 6 mm of the d.u.t. figure 2. test circuit, timing, and voltage definitions for the differential output signal y z input (see note a) c l = 10 pf (2 places) (see note b) 49.9 w 1% (2 places) v oc a a v oc v oc(pp) (see note c) v oc(ss) 0 3 v notes: a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, pulse repetition rate (prr) = 50 mpps, pulse width = 10 0.2 ns. b. c l includes instrumentation and fixture capacitance within 6 mm of the d.u.t. c. the measurement of v oc(pp) is made on test equipment with a 3 db bandwidth of at least 300 mhz. figure 3. test circuit and definitions for the driver common-mode output voltage
sn55lvds31, SN65LVDS31, sn65lvds3487, sn65lvds9638 high-speed differential line drivers slls261f july 1997 revised march 2000 9 post office box 655303 ? dallas, texas 75265 parameter measurement information y z inputs (see note a) c l = 10 pf (2 places) (see note b) 49.9 w 1% (2 places) g g 1.2 v t pzh t phz t pzl t plz 2 v 1.4 v 0.8 v 100%, @ 1.4 v 1.4 v 2 v 0.8 v 50% 0%, 1.2 v 0%, @ 1 v 100%, 1.2 v 50% g, 1,2en, or 3,4en g v oy or v oz v oz or v oy a at 2 v, g at v cc and input to g or g at gnd and input to g for 'lvds31 only a at 0.8 v, g at v cc and input to g or g at gnd and input to g for 'lvds31 only v oy v oz 0.8 v or 2 v 1,2en or 3,4en notes: a. all input pulses are supplied by a generator having the following characteristics: t r or t f < 1 ns, pulse repetition rate (prr) = 0.5 mpps, pulse width = 500 10 ns. b. c l includes instrumentation and fixture capacitance within 6 mm of the d.u.t. figure 4. enable and disable time circuit and definitions
sn55lvds31, SN65LVDS31, sn65lvds3487, sn65lvds9638 high-speed differential line drivers slls261f july 1997 revised march 2000 10 post office box 655303 ? dallas, texas 75265 typical characteristics figure 5 four drivers loaded per figure 3 and switching simultaneously. 29 27 19 15 50 100 supply current ma 31 33 f frequency mhz sn55lvds31, SN65LVDS31 supply current vs frequency 35 150 200 21 v cc = 3.6 v i cc v cc = 3.3 v 25 23 17 v cc = 3 v figure 6 1.5 1.4 1.2 1 1.7 1.9 40 20 0 low-to-high propagation delay time vs free-air temperature 20 40 t a free-air temperature c v cc = 3 v v cc = 3.6 v 1.8 1.6 1.3 1.1 60 80 100 v cc = 3.3 v low-to-high propagation delay time ns t plh figure 7 high-to-low propagation delay time vs free-air temperature 1.5 1.4 1.2 1 1.7 1.9 40 20 0 20 40 t a free-air temperature c v cc = 3 v 1.8 1.6 1.3 1.1 60 80 100 v cc = 3.3 v v cc = 3.6 v t phl high-to-low propagation delay time ns
sn55lvds31, SN65LVDS31, sn65lvds3487, sn65lvds9638 high-speed differential line drivers slls261f july 1997 revised march 2000 11 post office box 655303 ? dallas, texas 75265 applications information the devices are generally used as building blocks for high-speed point-to-point data transmission where ground differences are less than 1 v. devices can interoperate with rs-422, pecl, and ieee-p1596. drivers/receivers approach ecl speeds without the power and dual supply requirements. 10 1 0.1 transmission distance m 100 signaling rate mbps transmission distance vs signaling rate 10 100 1000 5% jitter (see note a) 30% jitter (see note a) 24 awg utp 96 w (pvc dielectric) note a: this parameter is the percentage of distortion of the unit interval (ui) with a pseudo-random data pattern. figure 8. typical transmission distance versus signaling rate 1a 1y 1z g 2z 2y 2a gnd v cc 4a 4y 4z g 3z 3y 3a 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 z o = 100 w z o = 100 w z o = 100 w z o = 100 w 3.3 v 0.1 m f (see note a) 0.001 m f (see note a) v cc see note b notes: a. place a 0.1 m f and a 0.001 m f z5u ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between v cc and the ground plane. the capacitors should be located as close as possible to the device terminals. b. unused enable inputs should be tied to v cc or gnd as appropriate. figure 9. typical application circuit schematic
sn55lvds31, SN65LVDS31, sn65lvds3487, sn65lvds9638 high-speed differential line drivers slls261f july 1997 revised march 2000 12 post office box 655303 ? dallas, texas 75265 applications information 1/4 'lvds31 'lvds32 500 w 500 w 20 k w 20 k w 3.3 v 500 w 500 w 20 k w 20 k w 3.3 v 7 k w 7 k w 10 k w 3.3 k w twisted-pair b only strb/data_tx strb/data_enable data/strobe 1 arb_rx 2 arb_rx port_status tpbias on twisted-pair a 55 w 55 w 5 k w vg on twisted-pair b tp tp 3.3 v notes: a. resistors are leadless thick-film (0603) 5% tolerance. b. decoupling capacitance is not shown but recommended. c. v cc is 3 v to 3.6 v. d. the differential output voltage of the 'lvds31 can exceed that specified by ieee1394. figure 10. 100 mbps ieee1394 transceiver
sn55lvds31, SN65LVDS31, sn65lvds3487, sn65lvds9638 high-speed differential line drivers slls261f july 1997 revised march 2000 13 post office box 655303 ? dallas, texas 75265 applications information 1a 1y 1z g 2z 2y 2a gnd v cc 4a 4y 4z g 3z 3y 3a 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 z o = 100 w z o = 100 w z o = 100 w z o = 100 w 3.6 v 0.1 m f (see note a) v cc see note b 1n645 (2 places) 0.01 m f 5 v note a: place a 0.1 m f z5u ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between v cc and the ground plane. the capacitor should be located as close as possible to the device terminals. figure 11. operation with a 5-v supply related information ibis modeling is available for this device. please contact the local ti sales office or the ti web site at www.ti.com for more information. for more application guidelines, please see the following documents: low-voltage differential signalling design notes (ti literature number slla014) interface circuits for tia/eia-644 (lvds) (slla038) reducing emi with lvds (slla030) slew rate control of lvds circuits (slla034) using an lvds receiver with rs-422 data (slla031) evaluating the lvds evm (slla033)
sn55lvds31, SN65LVDS31, sn65lvds3487, sn65lvds9638 high-speed differential line drivers slls261f july 1997 revised march 2000 14 post office box 655303 ? dallas, texas 75265 mechanical information d (r-pdso-g**) plastic small-outline package 14 pin shown 4040047 / d 10/96 0.228 (5,80) 0.244 (6,20) 0.069 (1,75) max 0.010 (0,25) 0.004 (0,10) 1 14 0.014 (0,35) 0.020 (0,51) a 0.157 (4,00) 0.150 (3,81) 7 8 0.044 (1,12) 0.016 (0,40) seating plane 0.010 (0,25) pins ** 0.008 (0,20) nom a min a max dim gage plane 0.189 (4,80) (5,00) 0.197 8 (8,55) (8,75) 0.337 14 0.344 (9,80) 16 0.394 (10,00) 0.386 0.004 (0,10) m 0.010 (0,25) 0.050 (1,27) 0 8 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). d. falls within jedec ms-012
sn55lvds31, SN65LVDS31, sn65lvds3487, sn65lvds9638 high-speed differential line drivers slls261f july 1997 revised march 2000 15 post office box 655303 ? dallas, texas 75265 mechanical information dgn (s-pdso-g8) powerpad ? plastic small-outline package 0,69 0,41 0,25 thermal pad (see note d) 0,15 nom gage plane 4073271/a 01/98 4,98 0,25 5 3,05 4,78 2,95 8 4 3,05 2,95 1 0,38 0,15 0,05 1,07 max seating plane 0,10 0,65 m 0,25 0 6 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions include mold flash or protrusions. d. the package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. this pad is electrical ly and thermally connected to the backside of the die and possibly selected leads. e. falls within jedec mo-187 powerpad is a trademark of texas instruments incorporated.
sn55lvds31, SN65LVDS31, sn65lvds3487, sn65lvds9638 high-speed differential line drivers slls261f july 1997 revised march 2000 16 post office box 655303 ? dallas, texas 75265 mechanical information fk (s-cqcc-n**) leadless ceramic chip carrier 4040140 / d 10/96 28 terminal shown b 0.358 (9,09) max (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) a no. of min max 0.358 0.660 0.761 0.458 0.342 (8,69) min (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32) (18,78) ** 20 28 52 44 68 84 0.020 (0,51) terminals 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 12 13 14 15 16 18 17 11 10 8 9 7 5 4 3 2 0.020 (0,51) 0.010 (0,25) 6 1 28 26 27 19 21 b sq a sq 22 23 24 25 20 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a metal lid. d. the terminals are gold plated. e. falls within jedec ms-004
sn55lvds31, SN65LVDS31, sn65lvds3487, sn65lvds9638 high-speed differential line drivers slls261f july 1997 revised march 2000 17 post office box 655303 ? dallas, texas 75265 mechanical information j (r-gdip-t**) ceramic dual-in-line package 1 20 0.290 (7,87) 0.310 0.975 (24,77) (23,62) 0.930 (7,37) 0.245 (6,22) (7,62) 0.300 18 16 14 pins ** 0.290 (7,87) 0.310 0.785 (19,94) (19,18) 0.755 (7,37) 0.310 (7,87) (7,37) 0.290 0.755 (19,18) (19,94) 0.785 0.245 (6,22) (7,62) 0.300 a 0.300 (7,62) (6,22) 0.245 a min a max b max b min c min c max dim 0.310 (7,87) (7,37) 0.290 (23,10) 0.910 0.300 (7,62) (6,22) 0.245 0 15 seating plane 0.014 (0,36) 0.008 (0,20) 4040083/d 08/98 c 8 7 0.020 (0,51) min b 0.070 (1,78) 0.100 (2,54) 0.065 (1,65) 0.045 (1,14) 14 pin shown 14 0.015 (0,38) 0.023 (0,58) 0.100 (2,54) 0.200 (5,08) max 0.130 (3,30) min notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a ceramic lid using glass frit. d. index point is provided on cap for terminal identification only on press ceramic glass frit seal only. e. falls within mil std 1835 gdip1-t14, gdip1-t16, gdip1-t18, gdip1-t20, and gdip1-t22.
sn55lvds31, SN65LVDS31, sn65lvds3487, sn65lvds9638 high-speed differential line drivers slls261f july 1997 revised march 2000 18 post office box 655303 ? dallas, texas 75265 mechanical information w (r-gdfp-f16) ceramic dual flatpack 0.235 (5,97) 0.355 (9,02) 0.355 (9,02) 0.235 (5,97) 9 8 16 1 0.745 (18,92) 0.245 (6,22) 0.004 (0,10) 0.026 (0,66) 0.015 (0,38) 0.015 (0,38) 0.045 (1,14) 0.371 (9,42) 0.006 (0,15) 0.045 (1,14) base and seating plane 0.025 (0,64) 0.019 (0,48) 0.440 (11,18) 0.285 (7,24) 0.085 (2,16) 1.025 (26,04) 4040180-3 / b 03/95 0.275 (6,99) 0.305 (7,75) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a ceramic lid using glass frit. d. index point is provided on cap for terminal identification only. e. falls within mil-std-1835 gdfp1-f16 and jedec mo-092ac
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